This course provides an introduction to system-on-chip (SoC) architecture, focusing on practical design methodologies and implementation strategies for modern embedded systems. Students will explore the fundamentals of digital and embedded SoC design, including Verilog-based hardware modeling, processor integration, bus protocols, and memory hierarchy. Emphasis will be placed on optimization techniques to enhance performance and power efficiency in mobile and resource-constrained environments. Students will finally gain experience in designing and analyzing SoC architectures, from digital building blocks to complete embedded systems, preparing them to address real-world challenges in SoC development.
Monday, 12:00-15:00 PM (Room A411, Engineering Bldg. or Recorded)
Wednesday 3:00-4:00 PM, or by appointment (Room C383-1, Engineering Bldg.)
| Week | Overview | Lecture Contents | Remark |
|---|---|---|---|
| 1 | Introduction | Introduction to Embedded SoC | |
| 2 | Digital System Review | Digital Building Blocks (Gate and Memory etc.) | |
| 3 | HDL Review I | Verilog HDL | |
| 4 | HDL Review II | Verilog Design Examples | |
| 5 | ARM Processor I | Development of ARM Processors | |
| 6 | Chuseok | No Class | |
| 7 | ARM Processor II | Design Example with Embedded ARM Processors | |
| 8 | Midterm Exam | ||
| 9 | Embedding Custom Blocks I | On-Chip Bus Protocols | |
| 10 | Embedding Custom Blocks II | Custom Slaves | |
| 11 | ISA I | Instruction Set Architecture (ISA) Review | |
| 12 | ISA II | RISC-V ISA and Datapath | |
| 13 | Optimization | Pipelining and Hazards | |
| 14 | RISC-V Design I | Single-Cycle Datapath Design | |
| 15 | RISC-V Design II | Pipelined Datapath Design | |
| 16 | Final Exam |