This course provides a comprehensive introduction to modern computer architecture, covering the fundamental principles that underlie the design and operation of computer systems. Students will begin with instruction set architecture (ISA) and progress through microarchitecture topics such as single-cycle, multicycle, and pipelined datapaths, hazard detection, and branch prediction. The course also explores memory hierarchy including cache and virtual memory, as well as I/O subsystems and communication protocols. By combining theory with practical exercises, students will develop a deep understanding of how hardware and software interact, and learn to analyze trade-offs in performance, power, and efficiency. Special emphasis will be placed on the RISC-V ISA as a case study, enabling students to connect architectural concepts with real-world processor design.
Tuesday, 9:00-10:30 PM (Recorded)
Thursday, 10:30 AM-12:00 PM (Room B106, New Engineering Bldg.)
Wednesday 3:00-4:00 PM, or by appointment (Room C383-1, Engineering Bldg.)
| Week | Overview | Lecture Contents | Remark |
|---|---|---|---|
| 1 | Introduction | Computer Architecture Overview | |
| 2 | ISA I | Introduction to Instruction Set Architecture (ISA) | |
| 3 | ISA II | RISC-V ISA | |
| 4 | Datapath I | Single-Cycle Datapath for RISC-V | Assignment 1 |
| 5 | Datapath II | Multicycle Datapath for RISC-V | |
| 6 | Chuseok | No Class | |
| 7 | Datapath III | Pipelined Datapath for RISC-V | Assignment 2 |
| 8 | Midterm Exam | ||
| 9 | Hazards | Structural, Control and Data Hazards | |
| 10 | Optimization | Branch Prediction | Assignment 3 |
| 11 | Interrupt | Interrupt and Interrupt Service Routine (ISR) | |
| 12 | I/Os | Bus, Protocols and I/Os | |
| 13 | Memory I | Memory Hierarchy | Assignment 4 |
| 14 | Memory II | Cache Concepts and Associativity | |
| 15 | Memory III | Virtual Memory Concepts and Translation Lookaside Buffer (TLB) | |
| 16 | Final Exam |