This course provides an in-depth introduction to digital integrated circuit (IC) design with a focus on AI-oriented hardware. Students will learn fundamental principles of CMOS technology, including device operation, gate-level design, and timing concepts, before progressing to advanced topics such as synthesis, layout, power optimization, and post-layout simulation. Through lectures and hands-on EDA tool practice, students will gain the ability to design, optimize, and evaluate digital circuits at both the logic and physical implementation levels. The final project will allow students to integrate these skills by implementing a digital system block suitable for AI applications. Tuesday in-person classes will cover the concepts on digital ICs and thursday recorded classes will mainly handlw how to use EDA tools.
Tuesday, 10:30 AM-12:00 PM (Room C481-1, Engineering Bldg.)
Thursday, 9:00-10:30 AM (Recorded)
Wednesday 3:00-4:00 PM, or by appointment (Room C383-1, Engineering Bldg.)
| Week | Overview | Lecture Contents | Remark |
|---|---|---|---|
| 1 | Introduction | Digital IC Introduction and Design Methodology | |
| 2 | CMOS Concept I | CMOS Basic and Synthesis I | |
| 3 | CMOS Concept II | Manufacturing and Synthesis II | |
| 4 | CMOS Concept III | CMOS Layout and Timing | Assignment 1 |
| 5 | Delay Concept I | Setup Time and Static Timing Analysis (STA) | |
| 6 | Chuseok | No Class | |
| 7 | Delay Concept II | Hold Time and Post-Synthesis Simulation | Assignment 2 |
| 8 | Midterm Exam | ||
| 9 | AI Hardware Review I | AI Model Operation and Floorplan | |
| 10 | AI Hardware Review II | AI Hardware Architecture and Placement | Assignment 3 |
| 11 | Physical Design | Interconnect and Clock Tree Synthesis (CTS) | |
| 12 | Power I | Power/Energy and Routing I | |
| 13 | Power II | Low Power Design and Routing II | Assignment 4 |
| 14 | Memory I | Memroy Design and RC Extraction | |
| 15 | Memory II | Memory Test and Post-Layout Simulation | |
| 16 | Final Exam |